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ADM2483BRWZ-REEL

Name: ADM2483BRWZ-REEL
Brand: Jinjiana Electronic Co.,Ltd.
Availability: InStock

Buy ADM2483BRWZ-REEL

ADM2483BRWZ-REEL Overview

The ADM2483 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on balanced, multipoint bus transmission lines. It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E). Using the iCoupler technology from Analog Devices, Inc., the ADM2483 combines a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or 3 V supply, and the bus side uses a 5 V supply only.

The ADM2483 is slew-limited to reduce reflections with improperly terminated transmission lines. The controlled slew rate limits the data rate to 500 kbps. The device's input impedance is 96 kΩ, allowing up to 256 transceivers on the bus. Its driver has an active-high enable feature. The driver differential outputs and receiver differential inputs are connected internally to form a differential input/output (I/O) port.

The ADM2483 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on balanced, multipoint bus transmission lines. It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E). Using the iCoupler technology from Analog Devices, Inc., the ADM2483 combines a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or 3 V supply, and the bus side uses a 5 V supply only.

The ADM2483 is slew-limited to reduce reflections with improperly terminated transmission lines. The controlled slew rate limits the data rate to 500 kbps. The device's input impedance is 96 kΩ, allowing up to 256 transceivers on the bus. Its driver has an active-high enable feature. The driver differential outputs and receiver differential inputs are connected internally to form a differential input/output (I/O) port.

Technical Data Of ADM2483BRWZ-REEL

Parameter	Min	Typ	Max	Unit	Test Conditions/Comments
DRIVER
Differential Outputs					R = ∞, see Figure 3
Differential Output Voltage, VOD			5	V	R = 50 Ω (RS-422), see Figure 3
	2		5	V	R = 27 Ω (RS-485), see Figure 3
	1.5		5	V	VTST = −7 V to +12 V, VDD1 ≥ 4.75,
	1.5		5	V	see Figure 4
Δ \|VOD \| for Complementary Output States Common-Mode Output Voltage, VOC Δ \|VOC \| for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low			0.2	V	R = 27 Ω or 50 Ω, see Figure 3
Logic Inputs			3	V	R = 27 Ω or 50 Ω, see Figure 3
Input High Voltage			0.2	V	R = 27 Ω or 50 Ω, see Figure 3
Input Low Voltage	−250		250	mA	−7 V ≤ VOUT ≤ +12 V
CMOS Logic Input Current (TxD, DE, RE, PV)	−250		250	mA	−7 V ≤ VOUT ≤ +12 V
	0.7 VDD1
			0.25 VDD1	V	TxD, DE, RE, PV
	−10		10	V	TxD, DE, RE, PV
		0.01		µA	TxD, DE, RE, PV = VDD1 or 0 V
RECEIVER
Differential Inputs	−200	−125			−7 V ≤ VCM ≤ +12 V
Differential Input Threshold Voltage, VTH	96	20	−30	mV	−7 V ≤ VCM ≤ +12 V
Input Hysteresis		150		mV	−7 V ≤ VCM ≤ +12 V
Input Resistance (A, B)				Ω	VIN = +12 V
Input Current (A, B)	VDD1 − 0.1 VDD1 − 0.4		0.125	mA	VIN = −7 V
RxD Logic Output			−0. 1	mA	IOUT = 20 µA, VA − VB = 0.2 V
Output High Voltage	7	VDD1 − 0.2			IOUT = 4 mA, VA − VB = 0.2 V
Output Low Voltage				V	IOUT = −20 µA, VA − VB = −0.2 V
Output Short-Circuit Current Three-State Output Leakage Current			0.1	V	IOUT = −4 mA, VA − VB = −0.2 V
			0.4	V	VOUT = GND or VCC
			85	V	0.4 V ≤ VOUT ≤ 2.4 V
			±1	mA
				µA
POWER SUPPLY CURRENT					4.5 V ≤ VDD1 ≤ 5.5 V, outputs unloaded,
Logic Side			2.5	mA	RE = 0 V
					2.7 V ≤ VDD1 ≤ 3.3 V, outputs unloaded,
			1.3	mA	RE = 0 V
Bus Side					Outputs unloaded, DE = 5 V
			2	mA	Outputs unloaded, DE = 0 V
			1.7	mA
COMMON-MODE TRANSIENT IMMUNITY 1	25			kV/µs	TxD = VDD1 or 0 V, VCM = 1 kV,
COMMON-MODE TRANSIENT IMMUNITY 1	25			kV/µs	transient magnitude = 800 V

Parameter	Min	Typ	Max	Unit	Test Conditions/Comments
DRIVER				kbps
Maximum Data Rate	500			ns	RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9 RL = 500 Ω, CL = 100 pF, see Figure 6 and Figure 11
Propagation Delay, tPLH, tPHL	250		620	ns	RL = 500 Ω, CL = 15 pF, see Figure 6 and Figure 11
Skew, tSKEW			40	ns
Rise/Fall Time, tR, tF	200		600	ns
Enable Time			1050	ns
Disable Time			1050
RECEIVER				ns	CL = 15 pF, see Figure 7 and Figure 10
Propagation Delay, tPLH, tPHL	400		1050	ns	CL = 15 pF, see Figure 7 and Figure 10
Differential Skew, tSKEW			250	ns	RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12
Enable Time		25	70	ns	RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12
Disable Time		40	70
POWER VALID INPUT				µs
Enable Time		1	2	µs
Disable Time		3	5